[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[commits] r7358 - in /trunk/libc: ./ sysdeps/powerpc/fpu/ sysdeps/powerpc/powerpc32/fpu/ sysdeps/unix/sysv/linux/powerpc/powerpc32/ sy...
- To: commits@xxxxxxxxxx
- Subject: [commits] r7358 - in /trunk/libc: ./ sysdeps/powerpc/fpu/ sysdeps/powerpc/powerpc32/fpu/ sysdeps/unix/sysv/linux/powerpc/powerpc32/ sy...
- From: joseph@xxxxxxxxxx
- Date: Mon, 17 Nov 2008 21:02:22 -0000
Author: joseph
Date: Mon Nov 17 13:02:22 2008
New Revision: 7358
Log:
Merge changes between r7325 and r7357 from /fsf/trunk.
Added:
trunk/libc/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c
- copied unchanged from r7357, fsf/trunk/libc/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c
trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S
- copied unchanged from r7357, fsf/trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S
trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S
- copied unchanged from r7357, fsf/trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S
trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S
- copied unchanged from r7357, fsf/trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S
trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S
- copied unchanged from r7357, fsf/trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S
Modified:
trunk/libc/ChangeLog
trunk/libc/NEWS
trunk/libc/sysdeps/powerpc/fpu/Makefile
trunk/libc/sysdeps/powerpc/fpu/feholdexcpt.c
trunk/libc/sysdeps/powerpc/fpu/fenv_libc.h
trunk/libc/sysdeps/powerpc/fpu/fesetenv.c
trunk/libc/sysdeps/powerpc/fpu/feupdateenv.c
trunk/libc/sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S
trunk/libc/sysdeps/powerpc/powerpc32/fpu/setjmp-common.S
trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
Modified: trunk/libc/ChangeLog
==============================================================================
--- trunk/libc/ChangeLog (original)
+++ trunk/libc/ChangeLog Mon Nov 17 13:02:22 2008
@@ -1,3 +1,49 @@
+2008-11-13 Ryan S. Arnold <rsa@xxxxxxxxxx>
+
+ [BZ #6411]
+ * sysdeps/powerpc/fpu/Makefile: Added test case tst-setcontext-fpscr.
+ * sysdeps/powerpc/fpu/feholdexcpt.c (_FPU_MASK_ALL): Define to replace
+ magic numbers.
+ * sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_register): Dynamically
+ choose mtfsf insn based on PPC_FEATURE_HAS_DFP.
+ (relax_fenv_state): Same as above.
+ (FPSCR_29): Reserve bit in ISA 2.05.
+ (FPSCR_NI): Provide define for compat.
+ * sysdeps/powerpc/fpu/fesetenv.c (_FPU_MASK_ALL): Define to replace
+ magic numbers.
+ * sysdeps/powerpc/fpu/feupdateenv.c (_FPU_MASK_ALL): Define to replace
+ magic numbers.
+ * sysdeps/powerpc/fpu/tst-setcontext-fpscr.c: New file. Test case to
+ test setcontext and swapcontext with dynamic 64-bit FPSCR detection.
+ * sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S (__longjmp): Adjust
+ access to hwcap to account for hwcap size increase to uint64_t.
+ * sysdeps/powerpc/powerpc32/fpu/setjmp-common.S (__sigsetjmp ):
+ Likewise.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
+ (*setcontext): Likewise.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S:
+ New file.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S:
+ New file.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
+ (*setcontext): dynamically select mtfsf insn based on
+ PPC_FEATURE_HAS_DFP. Adjust access to hwcap to account for hwcap size
+ increase to uint64_t.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
+ (*swapcontext): dynamically select mtfsf insn based on
+ PPC_FEATURE_HAS_DFP. Adjust access to hwcap to account for hwcap size
+ increase to uint64_t.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S:
+ New file.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S:
+ New file.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
+ (*setcontext): dynamically select mtfsf insn based on
+ PPC_FEATURE_HAS_DFP.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
+ (*swapcontext): dynamically select mtfsf insn based on
+ PPC_FEATURE_HAS_DFP.
+
2008-11-13 Ulrich Drepper <drepper@xxxxxxxxxx>
* version.h: Bump for 2.9 release.
Modified: trunk/libc/NEWS
==============================================================================
--- trunk/libc/NEWS (original)
+++ trunk/libc/NEWS Mon Nov 17 13:02:22 2008
@@ -1,9 +1,12 @@
-GNU C Library NEWS -- history of user-visible changes. 2008-10-31
+GNU C Library NEWS -- history of user-visible changes. 2008-11-17
Copyright (C) 1992-2007, 2008 Free Software Foundation, Inc.
See the end for copying conditions.
Please send GNU C library bug reports via <http://sources.redhat.com/bugzilla/>
using `glibc' in the "product" field.
+
+Version 2.10
+
Version 2.9
Modified: trunk/libc/sysdeps/powerpc/fpu/Makefile
==============================================================================
--- trunk/libc/sysdeps/powerpc/fpu/Makefile (original)
+++ trunk/libc/sysdeps/powerpc/fpu/Makefile Mon Nov 17 13:02:22 2008
@@ -5,3 +5,7 @@
# libm needs ld.so to access dl_hwcap
$(objpfx)libm.so: $(elfobjdir)/ld.so
endif
+
+ifeq ($(subdir),stdlib)
+tests += tst-setcontext-fpscr
+endif
Modified: trunk/libc/sysdeps/powerpc/fpu/feholdexcpt.c
==============================================================================
--- trunk/libc/sysdeps/powerpc/fpu/feholdexcpt.c (original)
+++ trunk/libc/sysdeps/powerpc/fpu/feholdexcpt.c Mon Nov 17 13:02:22 2008
@@ -1,5 +1,5 @@
/* Store current floating-point environment and clear exceptions.
- Copyright (C) 1997, 2005 Free Software Foundation, Inc.
+ Copyright (C) 1997, 2005, 2008 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -18,6 +18,8 @@
02111-1307 USA. */
#include <fenv_libc.h>
+#include <fpu_control.h>
+#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
int
feholdexcept (fenv_t *envp)
@@ -35,7 +37,7 @@
/* If the old env had any eabled exceptions, then mask SIGFPE in the
MSR FE0/FE1 bits. This may allow the FPU to run faster because it
always takes the default action and can not generate SIGFPE. */
- if ((old.l[1] & 0x000000F8) != 0)
+ if ((old.l[1] & _FPU_MASK_ALL) != 0)
(void)__fe_mask_env ();
/* Put the new state in effect. */
Modified: trunk/libc/sysdeps/powerpc/fpu/fenv_libc.h
==============================================================================
--- trunk/libc/sysdeps/powerpc/fpu/fenv_libc.h (original)
+++ trunk/libc/sysdeps/powerpc/fpu/fenv_libc.h Mon Nov 17 13:02:22 2008
@@ -21,6 +21,8 @@
#define _FENV_LIBC_H 1
#include <fenv.h>
+#include <ldsodefs.h>
+#include <sysdep.h>
libm_hidden_proto (__fe_nomask_env)
@@ -34,7 +36,13 @@
/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */
#define fesetenv_register(env) \
- ({ double d = (env); asm volatile ("mtfsf 0xff,%0" : : "f" (d)); })
+ do { \
+ double d = (env); \
+ if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
+ asm volatile ("mtfsf 0xff,%0,1,0" : : "f" (d)); \
+ else \
+ asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \
+ } while(0)
/* This very handy macro:
- Sets the rounding mode to 'round to nearest';
@@ -42,7 +50,12 @@
- Prevents exceptions from being raised for inexact results.
These things happen to be exactly what you need for typical elementary
functions. */
-#define relax_fenv_state() asm ("mtfsfi 7,0")
+#define relax_fenv_state() \
+ do { \
+ if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
+ asm ("mtfsfi 7,0,1"); \
+ asm ("mtfsfi 7,0"); \
+ } while(0)
/* Set/clear a particular FPSCR bit (for instance,
reset_fpscr_bit(FPSCR_VE);
@@ -122,9 +135,18 @@
FPSCR_UE, /* underflow exception enable */
FPSCR_ZE, /* zero divide exception enable */
FPSCR_XE, /* inexact exception enable */
+#ifdef _ARCH_PWR6
+ FPSCR_29, /* Reserved in ISA 2.05 */
+#else
FPSCR_NI /* non-IEEE mode (typically, no denormalised numbers) */
+#endif /* _ARCH_PWR6 */
/* the remaining two least-significant bits keep the rounding mode */
};
+
+#ifdef _ARCH_PWR6
+ /* Not supported in ISA 2.05. Provided for source compat only. */
+# define FPSCR_NI 29
+#endif /* _ARCH_PWR6 */
/* This operation (i) sets the appropriate FPSCR bits for its
parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
Modified: trunk/libc/sysdeps/powerpc/fpu/fesetenv.c
==============================================================================
--- trunk/libc/sysdeps/powerpc/fpu/fesetenv.c (original)
+++ trunk/libc/sysdeps/powerpc/fpu/fesetenv.c Mon Nov 17 13:02:22 2008
@@ -1,5 +1,6 @@
/* Install given floating-point environment.
- Copyright (C) 1997,99,2000,01,02,07 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1999, 2000, 2001, 2007, 2008
+ Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -18,7 +19,10 @@
02111-1307 USA. */
#include <fenv_libc.h>
+#include <fpu_control.h>
#include <bp-sym.h>
+
+#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
int
__fesetenv (const fenv_t *envp)
@@ -29,18 +33,18 @@
new.fenv = *envp;
old.fenv = fegetenv_register ();
- /* If the old env has no eabled exceptions and the new env has any enabled
- exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put
- the hardware into "precise mode" and may cause the FPU to run slower on
- some hardware. */
- if ((old.l[1] & 0x000000F8) == 0 && (new.l[1] & 0x000000F8) != 0)
+ /* If the old env has no enabled exceptions and the new env has any enabled
+ exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
+ hardware into "precise mode" and may cause the FPU to run slower on some
+ hardware. */
+ if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
(void)__fe_nomask_env ();
- /* If the old env had any eabled exceptions and the new env has no enabled
+ /* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not
generate SIGFPE. */
- if ((old.l[1] & 0x000000F8) != 0 && (new.l[1] & 0x000000F8) == 0)
+ if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
(void)__fe_mask_env ();
fesetenv_register (*envp);
Modified: trunk/libc/sysdeps/powerpc/fpu/feupdateenv.c
==============================================================================
--- trunk/libc/sysdeps/powerpc/fpu/feupdateenv.c (original)
+++ trunk/libc/sysdeps/powerpc/fpu/feupdateenv.c Mon Nov 17 13:02:22 2008
@@ -1,5 +1,6 @@
/* Install given floating-point environment and raise exceptions.
- Copyright (C) 1997,99,2000,01,07 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1999, 2000, 2001, 2007, 2008
+ Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Ulrich Drepper <drepper@xxxxxxxxxx>, 1997.
@@ -19,7 +20,10 @@
02111-1307 USA. */
#include <fenv_libc.h>
+#include <fpu_control.h>
#include <bp-sym.h>
+
+#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
int
__feupdateenv (const fenv_t *envp)
@@ -39,14 +43,14 @@
exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put
the hardware into "precise mode" and may cause the FPU to run slower on
some hardware. */
- if ((old.l[1] & 0x000000F8) == 0 && (new.l[1] & 0x000000F8) != 0)
+ if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
(void)__fe_nomask_env ();
/* If the old env had any eabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not
generate SIGFPE. */
- if ((old.l[1] & 0x000000F8) != 0 && (new.l[1] & 0x000000F8) == 0)
+ if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
(void)__fe_mask_env ();
/* Atomically enable and raise (if appropriate) exceptions set in `new'. */
Modified: trunk/libc/sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S
==============================================================================
--- trunk/libc/sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S (original)
+++ trunk/libc/sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S Mon Nov 17 13:02:22 2008
@@ -47,16 +47,16 @@
lwz r5,_rtld_global_ro@got(r5)
mtlr r6
cfi_same_value (lr)
- lwz r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
+ lwz r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r5)
# else
lwz r5,_dl_hwcap@got(r5)
mtlr r6
cfi_same_value (lr)
- lwz r5,0(r5)
+ lwz r5,4(r5)
# endif
# else
- lis r5,_dl_hwcap@ha
- lwz r5,_dl_hwcap@l(r5)
+ lis r5,(_dl_hwcap+4)@ha
+ lwz r5,(_dl_hwcap+4)@l(r5)
# endif
andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
beq L(no_vmx)
Modified: trunk/libc/sysdeps/powerpc/powerpc32/fpu/setjmp-common.S
==============================================================================
--- trunk/libc/sysdeps/powerpc/powerpc32/fpu/setjmp-common.S (original)
+++ trunk/libc/sysdeps/powerpc/powerpc32/fpu/setjmp-common.S Mon Nov 17 13:02:22 2008
@@ -98,14 +98,14 @@
cfi_same_value (lr)
# ifdef SHARED
lwz r5,_rtld_global_ro@got(r5)
- lwz r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
+ lwz r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r5)
# else
lwz r5,_dl_hwcap@got(r5)
- lwz r5,0(r5)
+ lwz r5,4(r5)
# endif
# else
- lis r6,_dl_hwcap@ha
- lwz r5,_dl_hwcap@l(r6)
+ lis r6,(_dl_hwcap+4)@ha
+ lwz r5,(_dl_hwcap+4)@l(r6)
# endif
andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
beq L(no_vmx)
Modified: trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
==============================================================================
--- trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S (original)
+++ trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S Mon Nov 17 13:02:22 2008
@@ -157,15 +157,15 @@
# ifdef SHARED
lwz r7,_rtld_global_ro@got(r7)
mtlr r8
- lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
+ lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
# else
lwz r7,_dl_hwcap@got(r7)
mtlr r8
- lwz r7,0(r7)
+ lwz r7,4(r7)
# endif
# else
- lis r7,_dl_hwcap@ha
- lwz r7,_dl_hwcap@l(r7)
+ lis r7,(_dl_hwcap+4)@ha
+ lwz r7,(_dl_hwcap+4)@l(r7)
# endif
andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
Modified: trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
==============================================================================
--- trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S (original)
+++ trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S Mon Nov 17 13:02:22 2008
@@ -1,5 +1,5 @@
/* Jump to a new context powerpc32 common.
- Copyright (C) 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -71,33 +71,34 @@
cmpwi r3,0
bne 3f /* L(error_exit) */
-#ifdef __CONTEXT_ENABLE_FPRS
-# ifdef __CONTEXT_ENABLE_VRS
-# ifdef PIC
+#ifdef PIC
mflr r8
-# ifdef HAVE_ASM_PPC_REL16
+# ifdef HAVE_ASM_PPC_REL16
bcl 20,31,1f
1: mflr r7
addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
-# else
+# else
bl _GLOBAL_OFFSET_TABLE_@local-4
mflr r7
-# endif
-# ifdef SHARED
+# endif
+# ifdef SHARED
lwz r7,_rtld_global_ro@got(r7)
mtlr r8
- lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
-# else
+ lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
+# else
lwz r7,_dl_hwcap@got(r7)
mtlr r8
- lwz r7,0(r7)
-# endif
-# else
- lis r7,_dl_hwcap@ha
- lwz r7,_dl_hwcap@l(r7)
-# endif
- andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+ lwz r7,4(r7)
+# endif
+#else
+ lis r7,(_dl_hwcap+4)@ha
+ lwz r7,(_dl_hwcap+4)@l(r7)
+#endif
+
+#ifdef __CONTEXT_ENABLE_FPRS
+# ifdef __CONTEXT_ENABLE_VRS
+ andis. r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
la r10,(_UC_VREGS)(r31)
beq 2f /* L(has_no_vec) */
@@ -199,7 +200,20 @@
/* Restore the floating-point registers */
lfd fp31,_UC_FREGS+(32*8)(r31)
lfd fp0,_UC_FREGS+(0*8)(r31)
- mtfsf 0xff,fp31
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r7,PPC_FEATURE_HAS_DFP
+ beq 7f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp31,1,0
+ b 8f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+7: mtfsf 0xff,fp31
+8:
+# endif /* _ARCH_PWR6 */
lfd fp1,_UC_FREGS+(1*8)(r31)
lfd fp2,_UC_FREGS+(2*8)(r31)
lfd fp3,_UC_FREGS+(3*8)(r31)
Modified: trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
==============================================================================
--- trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S (original)
+++ trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S Mon Nov 17 13:02:22 2008
@@ -1,5 +1,5 @@
/* Save current context and jump to a new context.
- Copyright (C) 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -143,33 +143,34 @@
stfd fp30,_UC_FREGS+(30*8)(r3)
stfd fp31,_UC_FREGS+(31*8)(r3)
stfd fp0,_UC_FREGS+(32*8)(r3)
-
-# ifdef __CONTEXT_ENABLE_VRS
-# ifdef PIC
+
+# ifdef PIC
mflr r8
-# ifdef HAVE_ASM_PPC_REL16
+# ifdef HAVE_ASM_PPC_REL16
bcl 20,31,1f
1: mflr r7
addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
-# else
+# else
bl _GLOBAL_OFFSET_TABLE_@local-4
mflr r7
-# endif
-# ifdef SHARED
+# endif
+# ifdef SHARED
lwz r7,_rtld_global_ro@got(r7)
mtlr r8
- lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
-# else
+ lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
+# else
lwz r7,_dl_hwcap@got(r7)
mtlr r8
- lwz r7,0(r7)
-# endif
-# else
- lis r7,_dl_hwcap@ha
- lwz r7,_dl_hwcap@l(r7)
+ lwz r7,4(r7)
# endif
- andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+# else
+ lis r7,(_dl_hwcap+4)@ha
+ lwz r7,(_dl_hwcap+4)@l(r7)
+# endif
+
+# ifdef __CONTEXT_ENABLE_VRS
+ andis. r6,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
la r10,(_UC_VREGS)(r3)
la r9,(_UC_VREGS+16)(r3)
@@ -309,8 +310,8 @@
# ifdef HAVE_ASM_PPC_REL16
bcl 20,31,5f
5: mflr r7
- addis r7,r7,_GLOBAL_OFFSET_TABLE_-1b@ha
- addi r7,r7,_GLOBAL_OFFSET_TABLE_-1b@l
+ addis r7,r7,_GLOBAL_OFFSET_TABLE_-5b@ha
+ addi r7,r7,_GLOBAL_OFFSET_TABLE_-5b@l
# else
bl _GLOBAL_OFFSET_TABLE_@local-4
mflr r7
@@ -318,14 +319,14 @@
mtlr r8
# ifdef SHARED
lwz r7,_rtld_global_ro@got(r7)
- lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r7)
+ lwz r7,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET+4(r7)
# else
lwz r7,_dl_hwcap@got(r7)
- lwz r7,0(r7)
+ lwz r7,4(r7)
# endif
# else
- lis r7,_dl_hwcap@ha
- lwz r7,_dl_hwcap@l(r7)
+ lis r7,(_dl_hwcap+4)@ha
+ lwz r7,(_dl_hwcap+4)@l(r7)
# endif
andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
la r10,(_UC_VREGS)(r31)
@@ -429,7 +430,20 @@
/* Restore the floating-point registers */
lfd fp31,_UC_FREGS+(32*8)(r31)
lfd fp0,_UC_FREGS+(0*8)(r31)
- mtfsf 0xff,fp31
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r7,PPC_FEATURE_HAS_DFP
+ beq 7f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp31,1,0
+ b 8f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+7: mtfsf 0xff,fp31
+8:
+#endif /* _ARCH_PWR6 */
lfd fp1,_UC_FREGS+(1*8)(r31)
lfd fp2,_UC_FREGS+(2*8)(r31)
lfd fp3,_UC_FREGS+(3*8)(r31)
Modified: trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S
==============================================================================
--- trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S (original)
+++ trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S Mon Nov 17 13:02:22 2008
@@ -1,5 +1,5 @@
/* Switch to context.
- Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -26,6 +26,15 @@
#include <asm/ptrace.h>
#include "ucontext_i.h"
#include <asm/errno.h>
+
+ .section ".toc","aw"
+.LC__dl_hwcap:
+#ifdef SHARED
+ .tc _rtld_global_ro[TC],_rtld_global_ro
+#else
+ .tc _dl_hwcap[TC],_dl_hwcap
+#endif
+ .section ".text"
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
ENTRY(__novec_setcontext)
@@ -62,10 +71,32 @@
cmpdi r3,0
bne L(nv_error_exit)
+# ifdef SHARED
+/* Load _rtld-global._dl_hwcap. */
+ ld r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
+# else
+ ld r5,0(r5) /* Load extern _dl_hwcap. */
+# endif
+
lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r5,PPC_FEATURE_HAS_DFP
+ beq 5f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+ b 6f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+5:
mtfsf 0xff,fp0
+6:
+# endif /* _ARCH_PWR6 */
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
@@ -189,15 +220,7 @@
#endif
- .section ".toc","aw"
-.LC__dl_hwcap:
-#ifdef SHARED
- .tc _rtld_global_ro[TC],_rtld_global_ro
-#else
- .tc _dl_hwcap[TC],_dl_hwcap
-#endif
.section ".text"
-
.machine "altivec"
ENTRY(__setcontext)
CALL_MCOUNT 1
@@ -241,7 +264,7 @@
# else
ld r5,0(r5) /* Load extern _dl_hwcap. */
# endif
- andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+ andis. r6,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
beq L(has_no_vec)
cmpdi r10,0
@@ -346,7 +369,22 @@
lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r5,PPC_FEATURE_HAS_DFP
+ beq 7f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+ b 8f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+7:
mtfsf 0xff,fp0
+8:
+# endif /* _ARCH_PWR6 */
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
Modified: trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S
==============================================================================
--- trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S (original)
+++ trunk/libc/sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S Mon Nov 17 13:02:22 2008
@@ -1,5 +1,5 @@
/* Save current context and install the given one.
- Copyright (C) 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -27,7 +27,16 @@
#include "ucontext_i.h"
#include <asm/errno.h>
+ .section ".toc","aw"
+.LC__dl_hwcap:
+#ifdef SHARED
+ .tc _rtld_global_ro[TC],_rtld_global_ro
+#else
+ .tc _dl_hwcap[TC],_dl_hwcap
+#endif
+
#if SHLIB_COMPAT (libc, GLIBC_2_3, GLIBC_2_3_4)
+ .section ".text"
ENTRY(__novec_swapcontext)
CALL_MCOUNT 2
#ifdef __ASSUME_NEW_RT_SIGRETURN_SYSCALL
@@ -157,10 +166,31 @@
cmpdi r0,0
bne L(nv_do_sigret)
+# ifdef SHARED
+/* Load _rtld-global._dl_hwcap. */
+ ld r8,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r8)
+# else
+ ld r8,0(r8) /* Load extern _dl_hwcap. */
+# endif
+
lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r8,PPC_FEATURE_HAS_DFP
+ beq 5f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+ b 6f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+5:
mtfsf 0xff,fp0
+6:
+#endif /* _ARCH_PWR6 */
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)
@@ -283,15 +313,7 @@
#endif
- .section ".toc","aw"
-.LC__dl_hwcap:
-#ifdef SHARED
- .tc _rtld_global_ro[TC],_rtld_global_ro
-#else
- .tc _dl_hwcap[TC],_dl_hwcap
-#endif
.section ".text"
-
.machine "altivec"
ENTRY(__swapcontext)
CALL_MCOUNT 2
@@ -409,7 +431,7 @@
la r10,(SIGCONTEXT_V_RESERVE+8)(r3)
la r9,(SIGCONTEXT_V_RESERVE+24)(r3)
- andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+ andis. r6,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
clrrdi r10,r10,4
beq L(has_no_vec)
@@ -540,7 +562,7 @@
# else
ld r8,0(r8) /* Load extern _dl_hwcap. */
# endif
- andis. r8,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
+ andis. r6,r8,(PPC_FEATURE_HAS_ALTIVEC >> 16)
beq L(has_no_vec2)
cmpdi r10,0
@@ -646,7 +668,21 @@
lfd fp0,(SIGCONTEXT_FP_REGS+(32*8))(r31)
lfd fp31,(SIGCONTEXT_FP_REGS+(PT_R31*8))(r31)
lfd fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
+# ifdef _ARCH_PWR6
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+# else
+ /* Availability of DFP indicates a 64-bit FPSCR. */
+ andi. r6,r8,PPC_FEATURE_HAS_DFP
+ beq 7f
+ /* Use the extended four-operand version of the mtfsf insn. */
+ mtfsf 0xff,fp0,1,0
+ b 8f
+ /* Continue to operate on the FPSCR as if it were 32-bits. */
+7:
mtfsf 0xff,fp0
+8:
+#endif /* _ARCH_PWR6 */
lfd fp29,(SIGCONTEXT_FP_REGS+(PT_R29*8))(r31)
lfd fp28,(SIGCONTEXT_FP_REGS+(PT_R28*8))(r31)
lfd fp27,(SIGCONTEXT_FP_REGS+(PT_R27*8))(r31)