[patches] dcbz bug, fix #2

[Nathan Sidwell <nathan@xxxxxxxxxxxxxxxx>]

Here's a reworking of the powerpc dcbz erratum patch.  This patch is localized 
to the two places where __cache_line_size is being set.  I've verified this 
stops the extraneous seg faults on 8xx hardware.

ok?

nathan
--
Nathan Sidwell    ::   http://www.codesourcery.com   ::         CodeSourcery
nathan@xxxxxxxxxxxxxxxx    ::     http://www.planetfall.pwp.blueyonder.co.uk

2007-06-11  Nathan Sidwell  <nathan@xxxxxxxxxxxxxxxx>
	    Mark Shinwell  <shinwell@xxxxxxxxxxxxxxxx>

	* sysdeps/unix/sysv/linux/powerpc/libc-start.c
	(__libc_start_main): Detect 8xx parts and clear
	__cache_line_size if detected.
	* sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
	(DL_PLATFORM_AUXV): Likewise.

Index: sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
===================================================================
--- sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c	(revision 173564)
+++ sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c	(working copy)
@@ -24,14 +24,26 @@
 extern int __cache_line_size;
 weak_extern (__cache_line_size)
 
-/* Scan the Aux Vector for the "Data Cache Block Size" entry.  If found
-   verify that the static extern __cache_line_size is defined by checking
-   for not NULL.  If it is defined then assign the cache block size
-   value to __cache_line_size.  */
+/* Scan the Aux Vector for the "Data Cache Block Size" entry.  If
+   found verify that the static extern __cache_line_size is defined by
+   checking for not NULL.  If it is defined then assign the cache
+   block size value to __cache_line_size.  This is used by memset to
+   optimize setting to zero.  We have to detect 8xx processors, which
+   have buggy dcbz implementations that cannot report page faults
+   correctly.  That requires reading SPR, which is a privileged
+   operation.  Fortunately 2.2.18 and later emulates PowerPC mfspr
+   reads from the PVR register.  */
 #define DL_PLATFORM_AUXV						      \
       case AT_DCACHEBSIZE:						      \
 	{								      \
 	  int *cls = & __cache_line_size;				      \
+	  if (__LINUX_KERNEL_VERSION >= 0x020218)			      \
+	    {								      \
+	      unsigned pvr = 0;						      \
+	      asm ("mfspr %0, 287" : "=r" (pvr));			      \
+	      if ((pvr & 0xffff0000) == 0x00500000)			      \
+	        cls = NULL;						      \
+	    }								      \
 	  if (cls != NULL)						      \
 	    *cls = av->a_un.a_val;					      \
 	}								      \
Index: sysdeps/unix/sysv/linux/powerpc/libc-start.c
===================================================================
--- sysdeps/unix/sysv/linux/powerpc/libc-start.c	(revision 173564)
+++ sysdeps/unix/sysv/linux/powerpc/libc-start.c	(working copy)
@@ -108,13 +108,27 @@ int
       rtld_fini = NULL;
     }
 
-  /* Initialize the __cache_line_size variable from the aux vector.  */
+  /* Initialize the __cache_line_size variable from the aux vector.
+     This is used by memset to optimize setting to zero.  We have to
+     detect 8xx processors, which have buggy dcbz implementations that
+     cannot report page faults correctly.  That requires reading SPR,
+     which is a privileged operation.  Fortunately 2.2.18 and later
+     emulates PowerPC mfspr reads from the PVR register.  */
   for (ElfW (auxv_t) * av = auxvec; av->a_type != AT_NULL; ++av)
     switch (av->a_type)
       {
       case AT_DCACHEBSIZE:
 	{
 	  int *cls = &__cache_line_size;
+	  
+	  if (__LINUX_KERNEL_VERSION >= 0x020218)
+	    {
+	      unsigned pvr = 0;
+	      
+	      asm ("mfspr %0, 287" : "=r" (pvr) :);
+	      if ((pvr & 0xffff0000) == 0x00500000)
+		cls = NULL;
+	    }
 	  if (cls != NULL)
 	    *cls = av->a_un.a_val;
 	}